SN54ABT651的技术资料
*State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
*ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
*Latch-Up Performance Exceeds 500 mA Per JESD 17
*Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25℃
*High-Drive Outputs (–32-mA IOH,
64-mA IOL)
*Multiplexed Real-Time and Stored Data
*Inverting Data Paths
*Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs
SN54ABT651的技术参数：
Supply voltage range, VCC . . . . . . . . . . . . . . . .. . . . . . . . .–0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . .–0.5 V to 7 V
Voltage range applied to any output in the high or power-off state,
VO . .. . ... .. –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT651 . .. .. .. 96 mA
SN74ABT651 .. .. . 128 mA
Input clamp current, IIK (VI < 0) . . . . . .. . . . . . . . . . . . . .. .. .. . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . ... .. . . .–50 mA
Package thermal impedance, θJA (see Note 2): DB package . ... 104℃/W
DW package .. .. 81℃/W
NT package .. .. . 67℃/W
PW package.......120℃/W
Storage temperature range, Tstg. . . . . . . . . . . . .. .. . . . .–65℃ to 150℃
SN54ABT651的产品描述：
These devices consist of bus-transceiver circuits,D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEBA and OEBA) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’ABT651 devices.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all the other data sources to the two sets of bus lines are at high impedance, each set remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver (B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver (A to B).
